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| P4C189 HIGH SPEED 16 x 4 STATIC CMOS RAM WITH INVERTING OUTPUTS FEATURES 16 x 4 Static RAM Fast Access Time - 35 ns Commercial and Industrial Available in the following packages: - 16-Pin PDIP Inverted Outputs 5V Power Supply 10% for both commercial and industrial temperature ranges. Separate I/O Fully static operation with equal access and cycle times 3-STATE outputs for data bus applications DESCRIPTION The P4C189 is a 64-bit high-speed Static RAM with a 16 x 4 organization. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. The output data is the complement of the written data. The P4C189 is offered in a 16-Pin DIP package. Devices are offered in both commercial and industrial temperature ranges. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (P7) Document # SRAM100 Rev OR 1 Revised October 2005 P4C189 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value - 0.5 to +7 - 0.5 to VCC +0.5 - 55 to +125 Unit V Symbol TBIAS TSTG I OUT Parameter Temperature Under Bias Storage Temperature DC Output Current Value - 55 to +125 - 65 to +150 20 Unit C C mA VTERM TA V C RECOMMENDED OPERATING CONDITIONS Grade(2) Commercial Industrial Ambient Temp 0C to 70C -40C to 85C Gnd 0V 0V Vcc 5.0V 10% 5.0V 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF Output Capacitance VOUT = 0V DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VOH VOL VIH VIL IIL IIH ISC ICC IL Parameter Output High Voltage Output Low Voltage Input High Level Input Low Level Input Low Current Input High Current Output Short Circuit Current Power Supply Current VIN = 0.5 V (except CS) VIN = 0.5 V (CS) VCC = Max, VIN = 2.7V VCC = Max., VOUT = 0.0V VCC = Max. Commercial Industrial -150 Test Conditions Min. VCC = Min., VIN = VIH or VIL, IOH = -3.0 mA VCC = Min., VIN = VIH or VIL, IOL = 24 mA 2.0 0.8 -0.6 -1.2 5 -60 55 70 50 A mA mA A 2.4 0.5 P4C189 Max. Unit V V V V mA Output Leakage Current VOUT = VCC, VCC = Max. Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7. Transition is measured 200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM100 Rev OR Page 2 of 8 P4C189 FUNCTIONAL DESCRIPTION An active LOW write enable (WE) controls the writing/ reading operation of the memory. When chip select (CS) and write enable (WE) are LOW, the information on data inputs (D0 through D3) is written into the addressed memory word. Reading is performed with chip select (CS) LOW and write enable (WE) HIGH. The information stored in the addressed word is read out on the inverting outputs (O0 through O3). The outputs of the memory go to an inactive high impedance state whenever chip select (CS) is HIGH, or during the write operation when write enable (WE) is LOW. TRUTH TABLE Mode Standby Read Write CS H L L WE X H L Output High Z DOUT High Z Notes: H = HIGH L = Low X = Don't Care HIGH Z = Implies outputs are disabled or off. This condition is defined as high impedance state. AC CHARACTERISTICS--READ CYCLE (VCC = 5V 10%, All Temperature Ranges)(2) Sym. t RC tAA tAC t OH tLZ t HZ Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z -35 Min 35 35 15 2 2 10 Max Unit ns ns ns ns ns ns TIMING WAVEFORM OF READ CYCLE NO. 1(5) Document # SRAM100 Rev OR Page 3 of 8 P4C189 TIMING WAVEFORM OF READ CYCLE NO. 2 (6) AC CHARACTERISTICS--WRITE CYCLE (VCC = 5V 10%, All Temperature Ranges)(2) Sym. tWC tCW tAW tAS tWP t AH tDW t DH tWZ tOW -35 Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 0 Min 35 15 15 0 15 2 15 2 15 Max Unit ns ns ns ns ns ns ns ns ns ns WE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9) Document # SRAM100 Rev OR Page 4 of 8 P4C189 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED)(9) CS Notes: 9. CS and WE must be LOW for WRITE cycle. 10. If CS goes HIGH simultaneously with WE high, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. Document # SRAM100 Rev OR Page 5 of 8 P4C189 ORDERING INFORMATION SELECTION GUIDE The P4C189 is available in the following temperature range, speed, and package options. Temperature Range Commercial Temperature Industrial Temperature Package Plastic DIP Plastic DIP Speed (ns) 35 -35PC -35PI Document # SRAM100 Rev OR Page 6 of 8 P4C189 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P7 16 (300 mil) Min Max 0.145 0.200 0.020 0.014 0.023 0.040 0.060 0.008 0.016 0.740 0.780 0.240 0.260 0.300 0.320 0.100 BSC 0.310 0.365 0.125 0.150 0 15 PLASTIC DUAL IN-LINE PACKAGE Document # SRAM100 Rev OR Page 7 of 8 P4C189 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR ISSUE DATE Oct-05 SRAM100 P4C189 HIGH SPEED 16 x 4 Static CMOS RAM with inverting outputs ORIG. OF CHANGE JDB DESCRIPTION OF CHANGE New Data Sheet Document # SRAM100 Rev OR Page 8 of 8 |
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